A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/hpca/HoP03
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2003
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A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns.
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On-chip Interconnects, Communication Model, Low-Contention Communication, Network Partitioning, Irregular Topology
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A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns.
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