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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hpca/IyengarTB96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Louise_Trevillyan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pradip_Bose>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vijay_S._Iyengar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FHPCA.1996.501174>
foaf:homepage <https://doi.org/10.1109/HPCA.1996.501174>
dc:identifier DBLP conf/hpca/IyengarTB96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FHPCA.1996.501174 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Representative Traces for Processor Models with Infinite Cache. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Louise_Trevillyan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pradip_Bose>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vijay_S._Iyengar>
swrc:pages 62-72 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/hpca/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/hpca/IyengarTB96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/hpca/IyengarTB96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/hpca/hpca1996.html#IyengarTB96>
rdfs:seeAlso <https://doi.org/10.1109/HPCA.1996.501174>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hpca>
dc:subject dynamic traces, timer, performance evaluation, processor design (xsd:string)
dc:title Representative Traces for Processor Models with Infinite Cache. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document