Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/hpca/SemeraroMBADS02
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Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.
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Multiple Clock Domain, Dynamic Voltage and Frequency Scaling, Off-Line Analysis Tool, Low Power, Dynamic Reconfiguration Algorithm
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Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.
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