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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hpcc/VillaAG05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francisco_J._Villa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_M._Garc%E2%88%9A%E2%89%A0a_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manuel_E._Acacio>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11557654%5F27>
foaf:homepage <https://doi.org/10.1007/11557654_27>
dc:identifier DBLP conf/hpcc/VillaAG05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11557654%5F27 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Francisco_J._Villa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_M._Garc%E2%88%9A%E2%89%A0a_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manuel_E._Acacio>
swrc:pages 213-222 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/hpcc/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/hpcc/VillaAG05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/hpcc/VillaAG05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/hpcc/hpcc2005.html#VillaAG05>
rdfs:seeAlso <https://doi.org/10.1007/11557654_27>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hpcc>
dc:title Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document