A Parallel Simulated Annealing Approach for Floorplanning in VLSI.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ica3pp/FangCCLHSH09
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/ica3pp/FangCCLHSH09
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Chih-Chia_Chen
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Chin-Chuan_Han
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jyh-Perng_Fang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Muhammad_T._Satria
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tung-Ju_Hsieh
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Wen-Yew_Liang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yang-Lang_Chang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-03095-6%5F29
>
foaf:
homepage
<
https://doi.org/10.1007/978-3-642-03095-6_29
>
dc:
identifier
DBLP conf/ica3pp/FangCCLHSH09
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1007%2F978-3-642-03095-6%5F29
(xsd:string)
dcterms:
issued
2009
(xsd:gYear)
rdfs:
label
A Parallel Simulated Annealing Approach for Floorplanning in VLSI.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Chih-Chia_Chen
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Chin-Chuan_Han
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jyh-Perng_Fang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Muhammad_T._Satria
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tung-Ju_Hsieh
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Wen-Yew_Liang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yang-Lang_Chang
>
swrc:
pages
291-302
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/ica3pp/2009
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/ica3pp/FangCCLHSH09/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/ica3pp/FangCCLHSH09
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/ica3pp/ica3pp2009.html#FangCCLHSH09
>
rdfs:
seeAlso
<
https://doi.org/10.1007/978-3-642-03095-6_29
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/ica3pp
>
dc:
subject
Floorplanning; FFA; Parallel Computing; Simulated Annealing; OpenMP
(xsd:string)
dc:
title
A Parallel Simulated Annealing Approach for Floorplanning in VLSI.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document