Neural Network Implementation in Reprogrammable FPGA Devices - An Example for MLP. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/icaisc/GorgonW06>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Marek_Gorgon>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Mateusz_Wrzesinski>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1007%2F11785231%5F3>
foaf:homepage	<https://doi.org/10.1007/11785231_3>
dc:identifier	DBLP conf/icaisc/GorgonW06 (xsd:string)
dc:identifier	DOI doi.org%2F10.1007%2F11785231%5F3 (xsd:string)
dcterms:issued	2006 (xsd:gYear)
rdfs:label	Neural Network Implementation in Reprogrammable FPGA Devices - An Example for MLP. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Marek_Gorgon>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Mateusz_Wrzesinski>
swrc:pages	19-28 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/icaisc/2006>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/icaisc/GorgonW06/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/icaisc/GorgonW06>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/icaisc/icaisc2006.html#GorgonW06>
rdfs:seeAlso	<https://doi.org/10.1007/11785231_3>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/icaisc>
dc:title	Neural Network Implementation in Reprogrammable FPGA Devices - An Example for MLP. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document