DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Almir_Maric>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Enio_Kaljic>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Pamela_Njemcevic>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICAT47117.2019.8938862>
foaf:homepage	<https://doi.org/10.1109/ICAT47117.2019.8938862>
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rdfs:label	DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Enio_Kaljic>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Pamela_Njemcevic>
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/icatech/icatech2019.html#KaljicMN19>
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dc:title	DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture. (xsd:string)
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