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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/ChatterjeePK95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mitrajit_Chatterjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wolfgang_Kunz>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1995.480135>
foaf:homepage <https://doi.org/10.1109/ICCAD.1995.480135>
dc:identifier DBLP conf/iccad/ChatterjeePK95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1995.480135 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label LOT: logic optimization with testability-new transformations using recursive learning. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mitrajit_Chatterjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wolfgang_Kunz>
swrc:pages 318-325 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/ChatterjeePK95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/ChatterjeePK95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1995.html#ChatterjeePK95>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1995.480135>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject EX-OR gates, combinational circuits, gate level, logic CAD, logic design, logic optimization with testability, multi-level logic circuits, random-pattern testability, recursive learning, tstfx (xsd:string)
dc:title LOT: logic optimization with testability-new transformations using recursive learning. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document