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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/CongHKP97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Kok_Koh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Zhigang_Pan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lei_He_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1997.643604>
foaf:homepage <https://doi.org/10.1109/ICCAD.1997.643604>
dc:identifier DBLP conf/iccad/CongHKP97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1997.643604 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Global interconnect sizing and spacing with consideration of coupling capacitance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Kok_Koh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Zhigang_Pan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lei_He_0001>
swrc:pages 628-633 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/CongHKP97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/CongHKP97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1997.html#CongHKP97>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1997.643604>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject GISS solutions, VLSI, asymmetric wire sizing, coupling capacitance, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties (xsd:string)
dc:title Global interconnect sizing and spacing with consideration of coupling capacitance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document