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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/CongK97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Kok_Koh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1997.643617>
foaf:homepage <https://doi.org/10.1109/ICCAD.1997.643617>
dc:identifier DBLP conf/iccad/CongK97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1997.643617 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Interconnect layout optimization under higher-order RLC model. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Kok_Koh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
swrc:pages 713-720 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/CongK97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/CongK97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1997.html#CongK97>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1997.643617>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject RATS trees, Steiner routings, bounded-radius Steiner trees, circuit optimisation, delay optimization, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, topology optimization, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization (xsd:string)
dc:title Interconnect layout optimization under higher-order RLC model. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document