Interconnect design for deep submicron ICs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccad/CongPHKK97
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1997
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Interconnect design for deep submicron ICs.
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required-arrival-time Steiner tree higher-order moment signal delay and integrity
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title
Interconnect design for deep submicron ICs.
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