Synthesis of customized loop caches for core-based embedded systems.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccad/CotterellV02
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/iccad/CotterellV02
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Frank_Vahid
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Susan_Cotterell
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F774572.774669
>
foaf:
homepage
<
https://doi.org/10.1145/774572.774669
>
dc:
identifier
DBLP conf/iccad/CotterellV02
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F774572.774669
(xsd:string)
dcterms:
issued
2002
(xsd:gYear)
rdfs:
label
Synthesis of customized loop caches for core-based embedded systems.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Frank_Vahid
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Susan_Cotterell
>
swrc:
pages
655-662
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/iccad/2002
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/iccad/CotterellV02/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/iccad/CotterellV02
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/iccad/iccad2002.html#CotterellV02
>
rdfs:
seeAlso
<
https://doi.org/10.1145/774572.774669
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/iccad
>
dc:
subject
architecture tuning, customized architectures, embedded systems, estimation, instruction fetching, loop cache, low energy, low power, memory hierarchy, synthesis, tuning
(xsd:string)
dc:
title
Synthesis of customized loop caches for core-based embedded systems.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document