A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccad/HongSZJSD96
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/iccad/HongSZJSD96
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ben_Song
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hao_Ji
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Wayne_Wei-Ming_Dai
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Wei_Hong_II
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Weikai_Sun
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhenhai_Zhu
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1996.569825
>
foaf:
homepage
<
https://doi.org/10.1109/ICCAD.1996.569825
>
dc:
identifier
DBLP conf/iccad/HongSZJSD96
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICCAD.1996.569825
(xsd:string)
dcterms:
issued
1996
(xsd:gYear)
rdfs:
label
A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ben_Song
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hao_Ji
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Wayne_Wei-Ming_Dai
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Wei_Hong_II
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Weikai_Sun
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhenhai_Zhu
>
swrc:
pages
381-386
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1996
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/iccad/HongSZJSD96/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/iccad/HongSZJSD96
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/iccad/iccad1996.html#HongSZJSD96
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICCAD.1996.569825
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/iccad
>
dc:
subject
3D VLSI interconnects, DRT, Dimension Reduction Technique, FastCap, SPICELINK, VLSI, capacitance extraction, dielectric layers, parallel signal lines
(xsd:string)
dc:
title
A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document