Analytical delay models for VLSI interconnects under ramp input. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/iccad/KahngMM96>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Andrew_B._Kahng>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kei_Masuko>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Sudhakar_Muddu>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1996.568907>
foaf:homepage	<https://doi.org/10.1109/ICCAD.1996.568907>
dc:identifier	DBLP conf/iccad/KahngMM96 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICCAD.1996.568907 (xsd:string)
dcterms:issued	1996 (xsd:gYear)
rdfs:label	Analytical delay models for VLSI interconnects under ramp input. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Andrew_B._Kahng>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kei_Masuko>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Sudhakar_Muddu>
swrc:pages	30-36 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1996>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/iccad/KahngMM96/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/iccad/KahngMM96>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/iccad/iccad1996.html#KahngMM96>
rdfs:seeAlso	<https://doi.org/10.1109/ICCAD.1996.568907>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject	Elmore delay, RLC interconnections, SPICE-computed delay, VLSI, VLSI interconnects, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect delays, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays (xsd:string)
dc:title	Analytical delay models for VLSI interconnects under ramp input. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document