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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/KuoWC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shih-Chieh_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shih-Hung_Weng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu-Min_Kuo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.2008.4681579>
foaf:homepage <https://doi.org/10.1109/ICCAD.2008.4681579>
dc:identifier DBLP conf/iccad/KuoWC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.2008.4681579 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label A novel sequential circuit optimization with clock gating logic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shih-Chieh_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shih-Hung_Weng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu-Min_Kuo>
swrc:pages 230-233 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/KuoWC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/KuoWC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad2008.html#KuoWC08>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.2008.4681579>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:title A novel sequential circuit optimization with clock gating logic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document