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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/LeeTW94>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._K._Wong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donald_T._Tang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jin-Fuw_Lee>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1994.629906>
foaf:homepage <https://doi.org/10.1109/ICCAD.1994.629906>
dc:identifier DBLP conf/iccad/LeeTW94 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1994.629906 (xsd:string)
dcterms:issued 1994 (xsd:gYear)
rdfs:label A timing analysis algorithm for circuits with level-sensitive latches. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._K._Wong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donald_T._Tang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jin-Fuw_Lee>
swrc:pages 743-748 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1994>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/LeeTW94/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/LeeTW94>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1994.html#LeeTW94>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1994.629906>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:title A timing analysis algorithm for circuits with level-sensitive latches. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document