Minimum area retiming with equivalent initial states. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/iccad/MaheshwariS97>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Naresh_Maheshwari>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1997.643523>
foaf:homepage	<https://doi.org/10.1109/ICCAD.1997.643523>
dc:identifier	DBLP conf/iccad/MaheshwariS97 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICCAD.1997.643523 (xsd:string)
dcterms:issued	1997 (xsd:gYear)
rdfs:label	Minimum area retiming with equivalent initial states. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Naresh_Maheshwari>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
swrc:pages	216-219 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1997>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/iccad/MaheshwariS97/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/iccad/MaheshwariS97>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/iccad/iccad1997.html#MaheshwariS97>
rdfs:seeAlso	<https://doi.org/10.1109/ICCAD.1997.643523>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject	Retiming, Sequential Circuits, VLSI, Design Automation, Timing Optimization, Area Optimization (xsd:string)
dc:title	Minimum area retiming with equivalent initial states. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document