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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/MathurCL95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anmol_Mathur>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._L._Liu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuang-Chien_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1995.480161>
foaf:homepage <https://doi.org/10.1109/ICCAD.1995.480161>
dc:identifier DBLP conf/iccad/MathurCL95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1995.480161 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Re-engineering of timing constrained placements for regular architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anmol_Mathur>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._L._Liu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuang-Chien_Chen>
swrc:pages 485-490 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/MathurCL95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/MathurCL95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1995.html#MathurCL95>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1995.480161>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject FPGAs, Xilinx 3000 FPGA architecture, design cycle, design debugging, design flow, design specification, engineering requirements, field programmable gate arrays, gate arrays, logic CAD, logic arrays, program debugging, regular architectures, systems re-engineering, timing constrained placements reengineering, timing performance (xsd:string)
dc:title Re-engineering of timing constrained placements for regular architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document