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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/OrshanskyMCKH00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chenming_Hu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kurt_Keutzer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Linda_Milor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Orshansky>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pinhong_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.2000.896452>
foaf:homepage <https://doi.org/10.1109/ICCAD.2000.896452>
dc:identifier DBLP conf/iccad/OrshanskyMCKH00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.2000.896452 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chenming_Hu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kurt_Keutzer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Linda_Milor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Orshansky>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pinhong_Chen>
swrc:pages 62-67 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/OrshanskyMCKH00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/OrshanskyMCKH00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad2000.html#OrshanskyMCKH00>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.2000.896452>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:title Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document