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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/PomeranzR95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1995.480204>
foaf:homepage <https://doi.org/10.1109/ICCAD.1995.480204>
dc:identifier DBLP conf/iccad/PomeranzR95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1995.480204 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Functional test generation for delay faults in combinational circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
swrc:pages 687-694 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/PomeranzR95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/PomeranzR95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1995.html#PomeranzR95>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1995.480204>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject combinational circuits, delay faults, delays, fault simulated, functional fault model, functional test generation, gate-level realizations, logic CAD, logic testing, test generation, test generators (xsd:string)
dc:title Functional test generation for delay faults in combinational circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document