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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/RuanSLCH99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Feipei_Lai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rung-Ji_Shang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shanq-Jang_Ruan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shyh-Jong_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xian-Jun_Huang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1999.810627>
foaf:homepage <https://doi.org/10.1109/ICCAD.1999.810627>
dc:identifier DBLP conf/iccad/RuanSLCH99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1999.810627 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label A bipartition-codec architecture to reduce power in pipelined circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Feipei_Lai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rung-Ji_Shang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shanq-Jang_Ruan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shyh-Jong_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xian-Jun_Huang>
swrc:pages 84-90 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/RuanSLCH99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/RuanSLCH99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1999.html#RuanSLCH99>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1999.810627>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:title A bipartition-codec architecture to reduce power in pipelined circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document