Power vs. delay in gate sizing: conflicting objectives? | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/iccad/SapatnekarC95>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Weitong_Chuang>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1995.480157>
foaf:homepage	<https://doi.org/10.1109/ICCAD.1995.480157>
dc:identifier	DBLP conf/iccad/SapatnekarC95 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICCAD.1995.480157 (xsd:string)
dcterms:issued	1995 (xsd:gYear)
rdfs:label	Power vs. delay in gate sizing: conflicting objectives? (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Weitong_Chuang>
swrc:pages	463-466 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1995>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/iccad/SapatnekarC95/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/iccad/SapatnekarC95>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/iccad/iccad1995.html#SapatnekarC95>
rdfs:seeAlso	<https://doi.org/10.1109/ICCAD.1995.480157>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject	CMOS digital integrated circuits, circuit CAD, circuit optimisation, convex programming, dynamic power, gate sizing, integrated circuit design, logic CAD, logic design, optimization problem, power-delay tradeoffs, short-circuit power (xsd:string)
dc:title	Power vs. delay in gate sizing: conflicting objectives? (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document