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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/SathyamurthySF95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Harsha_Sathyamurthy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_P._Fishburn>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1995.480158>
foaf:homepage <https://doi.org/10.1109/ICCAD.1995.480158>
dc:identifier DBLP conf/iccad/SathyamurthySF95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1995.480158 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Harsha_Sathyamurthy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_P._Fishburn>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
swrc:pages 467-470 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/SathyamurthySF95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/SathyamurthySF95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1995.html#SathyamurthySF95>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1995.480158>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject acyclic pipelines, area-delay tradeoff, circuit CAD, circuit optimisation, clock skew optimization, combinational circuits, cycle-borrowing, gate sizing, logic CAD, logic design, logic gates, pipeline processing, pipelined circuits, timing specifications (xsd:string)
dc:title Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document