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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/ShendePMH02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aditya_K._Prasad>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Igor_L._Markov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_P._Hayes>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vivek_V._Shende>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F774572.774625>
foaf:homepage <https://doi.org/10.1145/774572.774625>
dc:identifier DBLP conf/iccad/ShendePMH02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F774572.774625 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Reversible logic circuit synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aditya_K._Prasad>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Igor_L._Markov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_P._Hayes>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vivek_V._Shende>
swrc:pages 353-360 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/ShendePMH02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/ShendePMH02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad2002.html#ShendePMH02>
rdfs:seeAlso <https://doi.org/10.1145/774572.774625>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:title Reversible logic circuit synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document