Delay optimal partitioning targeting low power VLSI circuits. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/iccad/VaishnavP95>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Hirendu_Vaishnav>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Massoud_Pedram>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1995.480196>
foaf:homepage	<https://doi.org/10.1109/ICCAD.1995.480196>
dc:identifier	DBLP conf/iccad/VaishnavP95 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICCAD.1995.480196 (xsd:string)
dcterms:issued	1995 (xsd:gYear)
rdfs:label	Delay optimal partitioning targeting low power VLSI circuits. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Hirendu_Vaishnav>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Massoud_Pedram>
swrc:pages	638-643 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1995>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/iccad/VaishnavP95/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/iccad/VaishnavP95>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/iccad/iccad1995.html#VaishnavP95>
rdfs:seeAlso	<https://doi.org/10.1109/ICCAD.1995.480196>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject	VLSI, VLSI circuits, circuit CAD, clustering, delay optimal, integrated logic circuits, logic CAD, logic partitioning, partitioning, power dissipation (xsd:string)
dc:title	Delay optimal partitioning targeting low power VLSI circuits. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document