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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/VandenbergheBG97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abbas_El_Gamal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lieven_Vandenberghe>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephen_P._Boyd>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1997.643528>
foaf:homepage <https://doi.org/10.1109/ICCAD.1997.643528>
dc:identifier DBLP conf/iccad/VandenbergheBG97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1997.643528 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Optimal wire and transistor sizing for circuits with non-tree topology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abbas_El_Gamal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lieven_Vandenberghe>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephen_P._Boyd>
swrc:pages 252-259 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/VandenbergheBG97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/VandenbergheBG97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1997.html#VandenbergheBG97>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1997.643528>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject optimal circuit sizing, Elmore delay, crosstalk, clock distribution networks (xsd:string)
dc:title Optimal wire and transistor sizing for circuits with non-tree topology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document