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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/XiD96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joe_G._Xi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wayne_Wei-Ming_Dai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD.1996.569719>
foaf:homepage <https://doi.org/10.1109/ICCAD.1996.569719>
dc:identifier DBLP conf/iccad/XiD96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD.1996.569719 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Jitter-tolerant clock routing in two-phase synchronous systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joe_G._Xi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wayne_Wei-Ming_Dai>
swrc:pages 316-320 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/XiD96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/XiD96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1996.html#XiD96>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD.1996.569719>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter, jitter-tolerance, jitter-tolerant clock routing, manufacturing, near-zero skew, nonoverlapping interval, safety margin, simulated annealing, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, zero skew (xsd:string)
dc:title Jitter-tolerant clock routing in two-phase synchronous systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document