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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/XuXLL22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jin_Luo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ruifan_Xu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Youwei_Xiao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yun_Liang_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3508352.3549370>
foaf:homepage <https://doi.org/10.1145/3508352.3549370>
dc:identifier DBLP conf/iccad/XuXLL22 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3508352.3549370 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jin_Luo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ruifan_Xu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Youwei_Xiao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yun_Liang_0001>
swrc:pages 54:1-54:9 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/XuXLL22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/XuXLL22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad2022.html#XuXLL22>
rdfs:seeAlso <https://doi.org/10.1145/3508352.3549370>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:title HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document