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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad2/RzigaMGB19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Faten_Ouaja_Rziga>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kamel_Besbes>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Khaoula_Mbarek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sami_Ghedira>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCAD46983.2019.9037891>
foaf:homepage <https://doi.org/10.1109/ICCAD46983.2019.9037891>
dc:identifier DBLP conf/iccad2/RzigaMGB19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCAD46983.2019.9037891 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label A Verilog-A based RRAM Switching Model for Simulation and Analysis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Faten_Ouaja_Rziga>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kamel_Besbes>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Khaoula_Mbarek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sami_Ghedira>
swrc:pages 1-6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccad2/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad2/RzigaMGB19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad2/RzigaMGB19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad2/iccad2019.html#RzigaMGB19>
rdfs:seeAlso <https://doi.org/10.1109/ICCAD46983.2019.9037891>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccad2>
dc:title A Verilog-A based RRAM Switching Model for Simulation and Analysis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document