Buffer size trade-offs in input/output buffered ATM switches under various conditions.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icccn/ShiAZW95
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1995
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Buffer size trade-offs in input/output buffered ATM switches under various conditions.
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telecommunication traffic; buffer size trade-offs; input/output buffered ATM switches; nonlinear complex relationship; packet loss probability; average packet delay; traffic conditions; speed-up factors; VLSI design
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Buffer size trade-offs in input/output buffered ATM switches under various conditions.
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