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dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._Jayanthi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._Jamal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Varma>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCCNT54827.2022.9984597>
foaf:homepage <https://doi.org/10.1109/ICCCNT54827.2022.9984597>
dc:identifier DBLP conf/icccnt/VarmaCJPJ22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCCNT54827.2022.9984597 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label TCAD Simulation of a 10nm n-Channel Vertical Double Gate Silicon On Insulator MOSFET for Digital Applications. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Asisa_Kumar_Panigrahi>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._Jamal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Varma>
swrc:pages 1-6 (xsd:string)
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dc:title TCAD Simulation of a 10nm n-Channel Vertical Double Gate Silicon On Insulator MOSFET for Digital Applications. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document