A high performance bus and cache controller for PowerPC multiprocessing systems.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/AllenLC95
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1995
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A high performance bus and cache controller for PowerPC multiprocessing systems.
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microprocessor chips; multiprocessing systems; cache storage; system buses; coprocessors; performance evaluation; pipeline processing; high performance bus; cache controller; PowerPC; multiprocessing systems; PowerPC 620 microprocessor; system bus interface; ECC protected; co-processor; server-class systems; physical address bus; data bus; address transfer rates; pipelining; address snoop response; data transfer; cache coherency protocol; direct cache-to-cache data transfers; 2 GByte/s; 133 MHz; 128 MB
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A high performance bus and cache controller for PowerPC multiprocessing systems.
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