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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/AtaeiSG16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_E._Stine>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Matthew_R._Guthaus>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Samira_Ataei>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.2016.7753333>
foaf:homepage <https://doi.org/10.1109/ICCD.2016.7753333>
dc:identifier DBLP conf/iccd/AtaeiSG16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.2016.7753333 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_E._Stine>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Matthew_R._Guthaus>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Samira_Ataei>
swrc:pages 499-506 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/AtaeiSG16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/AtaeiSG16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd2016.html#AtaeiSG16>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.2016.7753333>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:title A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document