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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/ChangWW95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._K._Wong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._F._Wong_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yao-Wen_Chang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528836>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528836>
dc:identifier DBLP conf/iccd/ChangWW95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528836 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label FPGA global routing based on a new congestion metric. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._K._Wong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._F._Wong_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yao-Wen_Chang>
swrc:pages 372-378 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/ChangWW95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/ChangWW95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#ChangWW95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528836>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject field programmable gate arrays; programmable logic arrays; logic design; circuit layout CAD; FPGA global routing; congestion metric; routing capacity; switch block; switch-block capacity; congestion-control metric; graph modeling; global router; channel densities; congestion control (xsd:string)
dc:title FPGA global routing based on a new congestion metric. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document