Practical design and performance evaluation of completion detection circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/ChenG98
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1998
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Efficient BIST TPG design and test set compaction for delay testing via input reduction.
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Practical design and performance evaluation of completion detection circuits.
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Efficient BIST TPG design and test set compaction for delay testing via input reduction.
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Practical design and performance evaluation of completion detection circuits.
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