High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/ChoiKS99
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1999
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High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection.
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Low latency CORDIC architecture, Area optimization, Folded-transistor design
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High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection.
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