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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/FangA95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexander_Albicki>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Fang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528806>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528806>
dc:identifier DBLP conf/iccd/FangA95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528806 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Efficient testability enhancement for combinational circuit. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexander_Albicki>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Fang>
swrc:pages 168-179 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/FangA95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/FangA95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#FangA95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528806>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject combinational circuits; logic testing; automatic testing; performance evaluation; VLSI; built-in self test; testability enhancement; combinational circuit testing; XOR Chain Structure; controllability; observability; insertion points; testability analysis; random pattern resistant node source tracking; ISCAS85; benchmark circuits; hardware overhead; performance penalty; VLSI; automatic testing (xsd:string)
dc:title Efficient testability enhancement for combinational circuit. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document