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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/GhoshRJ95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Indradeep_Ghosh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528807>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528807>
dc:identifier DBLP conf/iccd/GhoshRJ95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528807 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Indradeep_Ghosh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
swrc:pages 173-179 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/GhoshRJ95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/GhoshRJ95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#GhoshRJ95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528807>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject design for testability; logic testing; integrated circuit testing; logic CAD; logic gates; automatic testing; high level synthesis; integrated circuit design; design for hierarchical testability; RTL circuits; behavioral synthesis; design for testability; gate-level sequential test generation; controller data path circuits; large data path bit-widths; minimal test hardware; register-transfer level design; system-level test set; high level synthesis (xsd:string)
dc:title Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document