Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/GhoshRJ95
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1995
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Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
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design for testability; logic testing; integrated circuit testing; logic CAD; logic gates; automatic testing; high level synthesis; integrated circuit design; design for hierarchical testability; RTL circuits; behavioral synthesis; design for testability; gate-level sequential test generation; controller data path circuits; large data path bit-widths; minimal test hardware; register-transfer level design; system-level test set; high level synthesis
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Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
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