Concurrent timing optimization of latch-based digital systems.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/HsiehLCG95
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1995
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Concurrent timing optimization of latch-based digital systems.
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logic design; optimisation; flip-flops; timing; hazards and race conditions; concurrent timing optimization; latch-based digital systems; digital system timing; retiming; intentional clock skew; wave pipelining; latch-based designed systems; multi-phase clocking; mixed integer linear program; integrated framework; resynchronization; latches insertion; race conditions; clock period
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Concurrent timing optimization of latch-based digital systems.
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