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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/HsiehLCG95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._Thomas_Gray>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hong-Yean_Hsieh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ralph_K._Cavin_III>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wentai_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528941>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528941>
dc:identifier DBLP conf/iccd/HsiehLCG95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528941 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Concurrent timing optimization of latch-based digital systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._Thomas_Gray>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hong-Yean_Hsieh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ralph_K._Cavin_III>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wentai_Liu>
swrc:pages 680-685 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/HsiehLCG95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/HsiehLCG95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#HsiehLCG95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528941>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject logic design; optimisation; flip-flops; timing; hazards and race conditions; concurrent timing optimization; latch-based digital systems; digital system timing; retiming; intentional clock skew; wave pipelining; latch-based designed systems; multi-phase clocking; mixed integer linear program; integrated framework; resynchronization; latches insertion; race conditions; clock period (xsd:string)
dc:title Concurrent timing optimization of latch-based digital systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document