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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/LuDS95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aiguo_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Erik_L._Dagless>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jonathan_M._Saul>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528841>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528841>
dc:identifier DBLP conf/iccd/LuDS95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528841 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label DART: delay and routability driven technology mapping for LUT based FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aiguo_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Erik_L._Dagless>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jonathan_M._Saul>
swrc:pages 409-414 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/LuDS95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/LuDS95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#LuDS95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528841>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject field programmable gate arrays; programmable logic arrays; delays; minimisation of switching nets; table lookup; logic design; DART; delay driven technology mapping; LUT based FPGAs; two-phased approach; routability directed delay-optimal mapping; stochastic routability analysis; delay-optimal mapping (xsd:string)
dc:title DART: delay and routability driven technology mapping for LUT based FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document