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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/NarayanananLGV95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_LaPotin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gopalakrishnan_Vijayan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Gupta_0003>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinod_Narayananan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528815>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528815>
dc:identifier DBLP conf/iccd/NarayanananLGV95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528815 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label PEPPER - a timing driven early floorplanner. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_LaPotin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gopalakrishnan_Vijayan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Gupta_0003>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinod_Narayananan>
swrc:pages 230-235 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/NarayanananLGV95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/NarayanananLGV95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#NarayanananLGV95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528815>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject integrated circuit layout; circuit layout CAD; computational complexity; timing; optimisation; CMOS integrated circuits; PEPPER; timing driven early floorplanner; chip complexities; early analysis; performance critical CMOS chips; interconnect delay; system design; performance; area; wireability; static timing analysis; floorplan optimization process (xsd:string)
dc:title PEPPER - a timing driven early floorplanner. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document