Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/Orailoglu96
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1996
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Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.
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112-117
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application specific integrated circuits; microarchitectural synthesis; dynamically reconfigurable ASICs; fault-tolerance scheme; band reconfiguration; multiple permanent faults; associated high-level synthesis procedure; graceful degradation; hardware rebinding; high-level synthesis
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Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.
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