[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/PandeyJBBYJ95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alok_Jain>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Derek_L._Beatty>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gary_York>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manish_Pandey>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Randal_E._Bryant>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Samir_Jain>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528929>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528929>
dc:identifier DBLP conf/iccd/PandeyJBBYJ95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528929 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Extraction of finite state machines from transistor netlists by symbolic simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alok_Jain>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Derek_L._Beatty>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gary_York>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manish_Pandey>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Randal_E._Bryant>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Samir_Jain>
swrc:pages 596-601 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/PandeyJBBYJ95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/PandeyJBBYJ95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#PandeyJBBYJ95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528929>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject circuit analysis computing; finite state machines; logic design; logic CAD; finite state machine extraction; transistor netlists; symbolic simulation; clock level finite state machines; FSMs; gate level representation; circuit clocking; output timing; simulation patterns; symbolic simulator; next state; output function; equivalent FSM; Ordered Binary Decision Diagrams; static storage structures; time multiplexed inputs; time multiplexed outputs (xsd:string)
dc:title Extraction of finite state machines from transistor netlists by symbolic simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document