Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/PomeranzR99
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Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
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bridging faults, circuit partitioning, fault simulation, stuck-at faults, test generation.
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Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
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