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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/SarmentaPW95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gill_A._Pratt>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luis_F._G._Sarmenta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephen_A._Ward>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528821>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528821>
dc:identifier DBLP conf/iccd/SarmentaPW95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528821 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Rational clocking [digital systems design]. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gill_A._Pratt>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luis_F._G._Sarmenta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephen_A._Ward>
swrc:pages 271-278 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/SarmentaPW95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/SarmentaPW95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#SarmentaPW95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528821>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject synchronisation; delays; clocks; minimisation of switching nets; logic design; rational clocking; independently-clocked digital subsystems; finite probability; synchronization failure; delays; phase relationship; logic design; digital systems design (xsd:string)
dc:title Rational clocking [digital systems design]. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document