A floating point radix 2 shared division/square root chip.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/SrinivasP95
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1995
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A floating point radix 2 shared division/square root chip.
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CMOS integrated circuits; floating point arithmetic; VLSI; IEEE standards; dividing circuits; floating point radix 2 shared division/square root chip; full-custom 1.2 micron CMOS VLSI chip; single precision IEEE 754 std. floating point numbers; square root algorithm; division algorithm; digit-by-digit schemes; quotient/root digit selection; 1.2 micron; 5.0 V; 66 MHz
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A floating point radix 2 shared division/square root chip.
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