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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccd/YungW95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Neil_C._Wilhelm>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_Yung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCD.1995.528826>
foaf:homepage <https://doi.org/10.1109/ICCD.1995.528826>
dc:identifier DBLP conf/iccd/YungW95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCD.1995.528826 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Caching processor general registers. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Neil_C._Wilhelm>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_Yung>
swrc:pages 307-312 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccd/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccd/YungW95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccd/YungW95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccd/iccd1995.html#YungW95>
rdfs:seeAlso <https://doi.org/10.1109/ICCD.1995.528826>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccd>
dc:subject cache storage; memory architecture; parallel architectures; caching processor general registers; register file; processor cycle time requirements; small register cache; register caching; performance model; windowed-register architectures (xsd:string)
dc:title Caching processor general registers. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document