Low power and high speed multiplication design through mixed number representations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iccd/ZhengA95
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1995
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Low power and high speed multiplication design through mixed number representations.
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digital arithmetic; redundant number systems; high speed multiplication; mixed number representations; low power multiplication; VLSI architecture; reduced switching; Sign-Magnitude; Redundant Binary adder; Booth decoder; Carry-Propagation-Free; Partial Products
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Low power and high speed multiplication design through mixed number representations.
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