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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icce-tw/HsiaoCHH21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jyun-Liang_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shen-Fu_Hsiao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiang-Ting_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi_Hsu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCE-TW52618.2021.9603254>
foaf:homepage <https://doi.org/10.1109/ICCE-TW52618.2021.9603254>
dc:identifier DBLP conf/icce-tw/HsiaoCHH21 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCE-TW52618.2021.9603254 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jyun-Liang_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shen-Fu_Hsiao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiang-Ting_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi_Hsu>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icce-tw/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icce-tw/HsiaoCHH21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icce-tw/HsiaoCHH21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icce-tw/icce-tw2021.html#HsiaoCHH21>
rdfs:seeAlso <https://doi.org/10.1109/ICCE-TW52618.2021.9603254>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icce-tw>
dc:title Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document