Optimizing Power IC Layouts by Simulation Tools.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icce-tw/HuangLCCHLL21
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Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/icce-tw/HuangLCCHLL21
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ching-Ho_Li
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Chun-Chih_Chen
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Gong-Kai_Lin
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jian-Hsing_Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kai-Chieh_Hsu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Li-Fan_Chen
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shao-Chang_Huang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICCE-TW52618.2021.9603082
>
foaf:
homepage
<
https://doi.org/10.1109/ICCE-TW52618.2021.9603082
>
dc:
identifier
DBLP conf/icce-tw/HuangLCCHLL21
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICCE-TW52618.2021.9603082
(xsd:string)
dcterms:
issued
2021
(xsd:gYear)
rdfs:
label
Optimizing Power IC Layouts by Simulation Tools.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ching-Ho_Li
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Chun-Chih_Chen
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Gong-Kai_Lin
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jian-Hsing_Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kai-Chieh_Hsu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Li-Fan_Chen
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shao-Chang_Huang
>
swrc:
pages
1-2
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/icce-tw/2021
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/icce-tw/HuangLCCHLL21/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/icce-tw/HuangLCCHLL21
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/icce-tw/icce-tw2021.html#HuangLCCHLL21
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICCE-TW52618.2021.9603082
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/icce-tw
>
dc:
title
Optimizing Power IC Layouts by Simulation Tools.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document